1. Field of the Invention
The present invention relates generally to semiconductor wafer fabrication, and more particularly, to a method for planarizing insulating layers on such substrates.
Planarization of semiconductor substrate surfaces during the fabrication of fine-geometry integrated circuits is necessary to improve both photolithographic feature resolution and dimensional control and to alleviate metallization discontinuity which may result from abrupt changes in topography.
Three methods are commonly employed for achieving such planarization. The simplest approach, referred to as doped oxide reflow, involves heating the wafer to a very high temperature, typically about 1000.degree. C., in order to cause an insulating layer to flow and become level. While suitable for some applications, such a high temperature technique cannot be used with devices having aluminum-based interconnections and/or shallow source and drain junctions. Thus, the method is unsuitable for fabrication of very large scale integration (VLSI) devices.
Two other commonly-employed methods for planarization involve the deposition of a sacrificial leveling layer, such as photoresist, to fill the voids and crevices which are present following application of an insulating layer. The flat surface created by the sacrificial layer is then etched back at a uniform rate to leave a generally flat layer of insulating material having a desired thickness. The first of these methods employs ion beam erosion of the sacrificial and insulating layers which, although workable, is a relatively slow tecnhique capable of removing only about 1000 .ANG. per minute. Thus, the technique is generally unsuitable for the removal of thick sacrificial layers, on the order of 20,000 to 40,000 .ANG., required to planarize metallization layers.
The second technique utilizes conventional high frequency low pressure batch plasma etching for removing the sacrificial layer. Such conventional batch etching techniques, however, are inherently non-uniform, causing both a loss of planarity across individual wafers as the etch proceeds and variations among different wafers, even though they are processed simultaneously. Thus, since the nature of a batch process requires that all wafers be processed for the same time, optimum control still results in some of the wafers being over-etched with others being under-etched.
For these reasons, it would be desirable to provide improved methods for planarizing substrate surfaces, particularly for planarizing insulating layers overlying uneven topographic features. It is further desirable that such methods be capable of planarizing relatively large and abrupt variations in the underlying topography, and that they be adaptable to wide variations in feature size and feature density on the wafer. Finally, the methods should be rapid so that there is little or no increase in the ovreall fabrication time and should provide for precise end point control to minimize over-etching/under-etching of the planarization and insulating layers.
2. Description of the Relevant Art
Planarization methods employing post-deposition doped oxide reflow are described in Bowling and Larrabee (1985) J. Electrochem. Soc. 132:141. Planarization techniques employing ion beam erosion of sacrificial and insulating layers are described in Johnson et al. (1982) App. Phys. Lett. 40:636; Johnson et al. (1983) J. Vac. Sci. Technol. B1:487; and Mogami et al. (1985) J. Vac. Sci. Technol. B3:857. Methods for planarization using a plasma etch of a sacrificial layer are described in Adams and Capio (1981) J. Electrochem. Soc. 128:423. See also, U.S. Pat. Nos. 4,358,356 and 4,377,438 which discuss alternate planarization techniques.